1. Field of the Invention
The present invention relates to a method for manufacturing a Bi-CMOS semiconductor device and, more particularly to a fabricating method for producing a high speed and high packing density semiconductor device (Bi-CMOS) through the combination of bipolar device to be used in high speed circuits and complementary metal oxide semiconductor (CMOS) device to be used in high packing density circuits.
2. Description of the Prior Art
Generally, to fabricate computer system, communication system or the like to be used for processing information, various integrated-circuits comprising a plurality of semiconductor devices are required. In addition, in the case that information to be performed in such system are composed of a large scale of capacitance, it is well known that a plurality of high speed and high packing density semiconductor devices possible to rapidly process a large scale of information are necessary to fabricate such integrated-circuits.
Semiconductor devices used in large numbers to fabricate such circuits are classified into two types of devices, that is, bipolar device and MOS (metal oxide semiconductor) device. The former is used in high speed circuits due to high speed operating characteristic, but can not be manufactured in high packing density as compared to a MOS device. The latter is used in high packing density circuits due to its small size, but can not be operated in high speed due to large junction capacitance.
Accordingly, to manufacture a high speed and high packing density semiconductor device, there is provided Bi-MOS semiconductor device in which a high speed bipolar transistor and a high packing density MOS device are formed on the same substrate. In recent years, the trend in the design of integrated devices is that various types of Bi CMOS's having CMOS device instead of MOS device have been developed in order to reduce power consumption of the semiconductor device.
Such Bi-CMOS semiconductor device can be applied to integrated circuits necessary for high speed, high packing density and low consumption of power source.
Prior Bi-CMOS semiconductor device with a standard buried collector (hereinafter, referred to as "SBC") bipolar transistor is shown in FIG. 1. Since the SBC bipolar transistor is manufactured by means of a device isolation method based on P-N junction, decreasing the width of a bipolar transistor is largely restricted by a lateral diffusion and the occurrence of a depletion area therein, and problem occurs in operating speed of a device due to the increment of resistance or capacitance.
In order to solve the said problem which may be occurred in the prior Bi CMOS, another prior Bi-CMOS semiconductor device with a polysilicon self-aligned (hereinafter, referred to as "PSA") bipolar transistor has been already fabricated. The technology of manufacturing the prior Bi-CMOS semiconductor device with PSA bipolar transistor is disclosed in U.S. Pat. Nos. 4,868,135, 4,737,472, and U.S. Pat. No. 4,954,458.
In details, the respective patents show a process for manufacturing Bi-CMOS semiconductor devices wherein the bipolar transistor is formed by means of a device isolation method based on an oxide film (SiO.sub.2) instead of P-N junction, and the emitter and base of such bipolar device are self-aligned by means of polysilicon film, and thus the size and capacitance of the PSA bipolar transistor can be largely decreased as compared to SBC bipolar transistor and integration can be more improved.
However, in the Bi-CMOS semiconductor device with PSA bipolar transistor manufactured by the prior technology as shown FIG. 2, since the width of inactive base region 1 with in the PSA bipolar transistor and the widths of the base and collector thereof are large, and junction capacitance between base and collector thereof is increases, problem occurs in operating speed of the Bi-CMOS semiconductor device.